Japan’s Dai Nippon Printing has unexpectedly set its sights on a market where until now one name has reigned supreme — ASML. The Dutch company controls around 90% of the global lithography equipment market and effectively holds a monopoly on EUV scanners, without which the most advanced chips are impossible. All modern electronics — from AI data centers to smartphones — quite literally depend on a single company and its machines.
On 9 December, Dai Nippon Printing announced in a press release that it has developed a template for nanoimprint lithography (NIL) with 10 nm line width. According to the company’s estimates, this resolution corresponds to 1.4 nm logic — the very node that TSMC, Samsung and other manufacturers are now striving to reach.
The key feature of the template is the combination of DNP’s experience in photomasks with Self-Aligned Double Patterning (SADP). First, a base pattern is formed; then, through film deposition and etching, the line density is effectively doubled. The result is an ultrathin “stamp” capable of transferring onto the wafer a pattern with the pitch required for the 1.4 nm class.
DNP also claims that using this technology can cut energy consumption by up to 90%. In an industry where a single EUV scanner draws megawatts of power, this is a striking statement at the very least. The templates are currently being evaluated by potential customers; DNP plans to move to mass production by 2027.
The tools are manufactured at Canon plants, and the companies state they will be “an order of magnitude cheaper” than EUV equipment from ASML (that is, roughly ten times cheaper). It would be wrong to call the technology a complete novelty, but until recently NIL was considered unsuitable for 2 nm and below. Apparently, Dai Nippon Printing has managed to resolve this bottleneck.
In effect, DNP is putting into Canon’s hands the missing element: an ultrathin “stamp” that can be inserted into an existing “stamping machine” to try to replace part of the most expensive and power-hungry EUV steps.
This all sounds extremely optimistic, which makes it worth recalling the possible caveats.
First, it is a contact technology: the template is physically pressed against the wafer. Any speck of dust between them guarantees that the entire imprint will be defective.
Second, it is more difficult to ensure precise overlay of multiple layers in complex multilayer logic structures.
Third, the throughput of NIL tools is noticeably lower than that of modern EUV scanners. To achieve the same number of wafers per hour, more machines will be needed — and that eats into part of the gains in cost and energy.
That is why neither DNP nor Canon is promising “the end of ASML’s era”. DNP’s press materials carefully state that the new NIL template can replace part of the EUV lithography process in the production of 1.4 nm-class chips. The idea is hybrid lines, where NIL takes over some of the most expensive and energy-intensive steps, while the critical layers remain on EUV.
But even such a partial scenario already represents a serious challenge to the current order of things. If the Japanese pair DNP + Canon manages to prove that part of a 1.4 nm-class process can be done more cheaply and at a fraction of the energy, the world will not get a full-fledged replacement for ASML but it will get an alternative. And at the same time, a way to reduce the carbon footprint and energy consumption of one of the most power-hungry stages of chip production.
